An analog-to-digital converter (ADC) is a system that converts an analog input signal into a digital output signal. One way to achieve such analog to digital conversion is by using a successive approximation analog-to-digital converter (SAR ADC). An SAR ADC performs successive comparison of input voltage signals to generated analog signals at each conversion cycle. The result of each comparison is used to generate the final output of digital signals, which is the digital representation of the analog input voltage signals. In typical SAR ADCs, these comparisons are performed by one or more comparators. If the analog signals to be compared are sufficiently close to each other in amplitude, the comparator may not be able to determine a digital output (i.e. logic level of 0 or 1) within the time required for proper operation. As a result, the SAR ADC falls into a metastable state and may react in unpredictable ways.
In a conventional SAR ADC, a metastability detector may use a timer circuit and memory element to detect a metastability event. For example, if a comparator does not make a decision within a certain amount of time, the bit is considered to be in a metastable state. When the metastability event is detected, existing detectors may stop the SAR ADC operation to prevent a system failure. However, these existing schemes are unreliable because the memory element itself can fall into a metastable state and therefore produce a false metastability error indication. In the event of the false metastability error indication, although all of the bits have enough time to be resolved from the metastability, the detectors may not check this condition because it stops the SAR ADC operation. Thus, it would be desirable to have methods and apparatuses that provide reliable metastability detection and correction under the circumstances of false metastability error indications.